There is an increasing need for transmitting large quantities of data at high speed with the rapid spread of televisions and DVD devices for digital broadcasting. Accordingly, standards on high-speed serial data interfaces such as DVI (Digital Visual Interface) and IEEE1394 attract attention at present, and there have been developed semiconductor integrated circuits for high-speed transmission, which are equipped with such interface technology to transmit differential data at high speed.
The high-speed transmission semiconductor integrated circuit which meets the standards such as DVI and IEEE1394 usually comprises a transmitting end for transmitting data and a receiving end for receiving data transmitted from a communication partner. The transmitting end of the high-speed transmission semiconductor integrated circuit differentially transmits data at high speeds ranging from 1 Gbit/s to 2.65 Gbit/s by a driver circuit. The receiving end differentially receives the high-speed data transmitted from the communication partner (transmitting end) by a receiver circuit. While each of the transmitting end and the receiving end may be formed as one chip of a semiconductor integrated circuit, the transmitting end and the receiving end may be formed integrally on one chip of a semiconductor integrated circuit.
Tests for the high-speed transmission semiconductor integrated circuit are performed as follows. On the transmitting end, a signal output from a device-under-test semiconductor (hereinafter, referred to as a “DUT”) is input to a semiconductor tester (hereinafter, referred to as a “tester”), and a pattern collation between the sampled output signal and an expected value held by the tester is performed, thereby sorting out defectives. On the other hand, on the receiving end, initially the tester outputs a test clock of a frequency that is defined under the test specifications and test data at a transmission rate that is defined under the test specifications to operate the DUT. Then, the output signal from the DUT is input to the tester, and a pattern collation between the sampled output signal and the expected value held by the tester is performed, thereby sorting out defectives.
However, in recent years, the speed of data transmission in the high-speed transmission semiconductor integrated circuits is increased, and the transmission rate of the DUT exceeds a testing capability of the tester. To avoid problems of the transmission rate or the frequency, the high-speed semiconductor integrated circuit frequently adopts as a BIST (Built In Self Test), a loopback system in which data transmitted from the DUT at the transmitting end are received by the DUT at the receiving end as they are.
A conventional test circuit employing the loopback system will be described with reference to FIG. 6.
FIG. 6 is a block diagram illustrating a construction of the conventional test circuit of a high-speed transmission semiconductor integrated circuit and a conventional test method.
In FIG. 6, numeral 100f denotes a DUT which has a transmitting-end test circuit 110f for conducting a test on a transmitting function and a receiving-end test circuit 120f for conducting a test on a receiving function. Numeral 200 denotes a tester for testing the DUT 100f. 
The transmitting-end test circuit 110f comprises a PLL 117 which controls the phase of a test clock CK1 that is input from the tester 200 through a clock input terminal 131, for generating a PLL clock CKp5, a parallel/serial conversion unit (hereinafter, referred to as a “P/S”) 118 for converting a 10-bit parallel input signal Din1 that is input through a test data input terminal 132, into serial data, and a driver 115 which converts the serial signal into a high-speed small-amplitude signal and outputs loop data D110 to the outside of the DUT 100f through a data output terminal 133.
The receiving-end test circuit 120f comprises a PLL 127 which controls the phase of the test clock CK1 that is input through a clock input terminal 134, for generating a PLL clock CKp6, a receiver 123 for receiving the loop data D110 input through a data input terminal 135, and a serial/parallel conversion circuit (hereinafter, referred to as an “S/P”) 128 which converts the received serial loop data D110 into a parallel signal and outputs output data Dout1 to the tester 200 through a data output terminal 136.
The tester 200 comprises a transmission part 210 which generates the clock CK1 and the input data Din1 for operating the DUT 100f at the testing and outputs the same to the DUT, a reception part 220 for receiving the output data Dout1 output from the DUT 100f, and a judgement part 230 which holds an expected value for the input data Din1 and performs a pattern collation between the output data Dout1 and the expected value, thereby judging whether or not the DUT is a conforming item that performs an expected operation.
Next, a description will be given of a method for testing the so-constructed DUT 100f comprising the transmitting-end test circuit 110f and the receiving-end test circuit 120f. 
Here, the description will be given taking a case where a communication function at an operating frequency 100 MHz and a transmission rate 1.0 Gbps, which is defined under the test specifications, is tested as an example.
To make the DUT 100f convert 10-bit parallel data into serial data and output the serial data at the transmission rate of 1.0 Gbps, the tester 200 is required to supply a test clock CK1 of 100 MHz and input data Din1 of 100 Mbps×10 bits to the DUT 100f. Thus, the transmission part 210 of the tester 200 generates the 100 MHz test clock CK1 and the 100 Mbps×10-bit input data Din1, and outputs the same to the DUT 100f. 
When the test clock CK1 and the input data Din1 are input to the transmitting-end test circuit 110f of the DUT 100f, the PLL 117 generates from the clock CK1, a PLL clock CKp5 of the same frequency as that of the clock CK1, and outputs the PLL clock CKp5 to the P/S 118. The P/S 118 samples parallelly inputted 100 Mbps×10-bit data Din1 with the PLL clock CKp5 to be converted into a serial signal. The driver 115 converts this serial signal into a high-speed small-amplitude signal of 1.0 Gbps, and outputs the loop data D110 to the outside of the DUT 100f through the data output terminal 133.
The 1.0 Gbps loop data D110 which have been output to the outside of the DUT 100f are input to the DUT 100f again through the data input terminal 135. Then, in the receiving-end test circuit 120f of the DUT 100f, the receiver 123 receives the loop data D110 and outputs the data to the S/P 128. The PLL 127 generates from the clock CK1, the PLL clock CKp6 of the same frequency as that of the clock CK1, and outputs the PLL clock CKp6 to the S/P 128. The S/P 128 samples the serially input loop data D110 with the PLL clock CKp6 to be converted into a 100 Mbps×10-bit parallel signal, and outputs the output data Dout1 to the tester 200 through the data output terminal 136.
The reception part 220 of the tester 200 receives the output data Dout1 output from the DUT 100f, and outputs the data to the judgement part 230. The judgement part 230 compares the output data Dout1 with the held expected value to judge whether or not the output data coincides with the expected value, and determines that the DUT is an conforming item when they coincide with each other, while determining that the DUT is defective when they do not coincide with each other.
Further, as a BIST test, there has been developed a method of automating a test by providing a semiconductor integrated circuit with a circuit for generating a test pattern and a circuit for conducting a test utilizing an operation result on the basis of the generated test pattern.
For example, Japanese Published Patent Application No. Hei.9-261692 discloses a signal processing circuit which comprises a test pattern generation means that generates a test pattern for testing an internal operation of the signal processing circuit, a test result detection means that detects a result obtained by testing the internal operation of the signal processing circuit according to the generated test pattern, and a test timing control means that controls operational timings of the test pattern generation means and the test result detection means on the basis of a sync signal supplied to the signal processing circuit. In this signal processing circuit, when a test mode is set for the signal processing circuit on the basis of an arbitrary operation setting condition, the test pattern generation mean generates a test pattern for the operation setting condition, and an expected value of the operation result of the signal processing circuit based on the test pattern is compared with the test result detected by the test result detection means, thereby testing the signal processing circuit. Since this signal processing circuit performs the generation of the test pattern and the testing based on the generated test pattern in itself, a detailed operation test inside the signal processing circuit can be conducted simply with no additional device being provided outside.
However, since the signal processing circuit disclosed in Japanese Published Patent Application No. Hei.9-261692 generates the test pattern by the test pattern generation means, it is required to supply a signal for setting the test mode and a sync signal from the outside. Thus, even when a DUT which converts 10-bit parallel data into serial data to be transmitted (such as the DUT 100f as shown in FIG. 6) is provided with the test pattern generation means for generating the test pattern, the test result detection means for detecting the result that is obtained by testing the internal operation of the signal processing circuit according to the generated test pattern, and the test timing control means for controlling the operational timings of the test pattern generation means and the test result detection means on the basis of the supplied sync signal, as described in Japanese Published Patent Application No. Hei.9-261692, a clock of the operating frequency that is defined under the test specifications and the signal for setting the test mode must be input to the signal processing circuit from a tester in a like manner as described for the test of the DUT 100f. 
However, at present, the maximum test frequency of testers which are in widespread use in a relatively affordable price range is approximately 200 Mhz. Thus, even when the test adopting the loopback system is conducted as BIST in the DUT which converts 10-bit parallel data into serial data to be transmitted, such a tester has no test capability when the transmission rate exceeds 2 Gbps, and accordingly the test cannot be carried out.
For example, when a test for assuring a transmission rate of 2 Gbps is conducted in the DUT which converts 10-bit parallel data into serial data to be transmitted, the tester needs the capability of inputting/outputting data at a rate of 200 Mbps, i.e., one tenth of the transmission rate, and inputting a clock of 200 MHz to the DUT. Further, in the case of DVI as an interface standard for digital televisions, the transmission rate reaches 2.65 Gbps, and thus the tester needs a transmission rata that is equal to or higher than 265 Mbps and an operating frequency that is equal to or higher than 265 MHz as a testing capability, to conduct a test for assuring the transmission rate of 2.65 Gbps.
However, such high-performance testers that satisfy these conditions are quite expensive and take much time to adjust a voltage, timing, or the like for maintaining the accuracy of the testers.
Therefore, it is preferable to test a high-speed transmission semiconductor integrated circuit without introducing a new high-performance tester.